To ensure the proper function of a chip design, the chip or a system with the chip may be simulated in its real environment. Verification environment may also be coupled with the simulation in order to verify the chip.
Coverage Driven Verification (CDV) is a well-recognized and successful technique for dynamic verification of hardware design. The CDV environment runs on a connected workstation. The workstation may be coupled to an emulator which emulates a design under test (DUT). It is desirable to perform the testing as fast as possible. Thus, the emulation of the DUT may be accelerated.
One problem associated with the CDV is that the complex generation, coverage and checking algorithms may not generally be accelerated alongside the design when the design is mapped to an emulator where the design under test is being accelerated. As a result, the emulation has to be executed at a speed slower than what is possible. This configuration leads to significantly reduced performance improvement from the emulator.
The performance is reduced because verification is performed on a general-purpose processor that frequently communicates with the design and involves a lot of computation. In addition, the emulator simulates at a faster speed when compared to the verification processes. In other words, the clock cycle required for the simulation takes less time than the processing involved for verification. As a result, the emulator has to wait in order for the verification processes to catch up.
In general, running verification environments on the emulator becomes more difficult in complex environments. The emulation environment uses specially-designed components to drive interfaces and then control these components from software running in an accelerated microprocessor. Testing in this manner is faster but does not benefit from the advantages of cover driven verification (CDV). CDV requires very complex algorithms to generate and monitor verification data, and these algorithms are generally impossible to accelerate. In order to get the advantages of increased speed, verification complexity has to be sacrificed.
A conventional approach uses transaction-based interfaces between the CDV environment and the design under test (DUT) running on the emulator. This approach reduces the quantity of traffic between the CDV environment and the emulator. This approach also potentially reduce the amount of traffic, which may improves the speed of the emulation. However, this approach still places a limit on the amount of data that can be communicated through the transaction-based interface. Thus, this approach is limited by the availability of specially-designed verification components that have the necessary transaction-based interface, as well as speed optimizations in the generation, coverage and checking components.